? semiconductor components industries, llc, 2014 july, 2014 ? rev. 1 1 publication order number: cm1213a?04so/d cm1213a-04so, SZCM1213A-04SO 4-channel low capacitance esd protection array product description cm1213a?04so has been designed to provide esd protection for electronic components or subsystems requiring minimal capacitive loading. this device is ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. each esd channel consists of a pair of diodes in series which steer the positive or negative esd current pulse to either the positive (v p ) or negative (v n ) supply rail. a zener diode is embedded between v p and v n , offering two advantages. first, it protects the v cc rail against esd strikes, and second, it eliminates the need for a bypass capacitor that would otherwise be needed for absorbing positive esd strikes to ground. this device will protect against esd pulses up to 8 kv per the iec 61000?4?2 standard. this device is particularly well-suited for protecting systems using high-speed ports such as usb 2.0, ieee1394 (firewire ? , ilink ), serial ata, dvi, hdmi and corresponding ports in removable storage, digital camcorders, dvd?rw drives and other applications where extremely low loading capacitance with esd protection are required in a small package footprint. features ? four channels of esd protection ? provides esd protection to iec61000?4?2 level 4 ? 8 kv contact discharge ? low channel input capacitance of 0.85 pf typical ? minimal capacitance change with temperature and voltage ? channel input capacitance matching of 0.02 pf typical is ideal for differential dignals ? zener diode protects supply rail and eliminates the need for external by-pass capacitors ? each i/o pin can withstand over 1000 esd strikes* ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb-free and rohs compliant applications ? usb2.0 ports at 480 mbps in desktop pcs, notebooks and peripherals ? ieee1394 firewire ? ports at 400 mbps/800 mbps ? dvi ports, hdmi ports in notebooks, set top boxes, digital tvs, lcd displays ? serial ata ports in desktop pcs and hard disk drives ? pci express ports ? general purpose high?speed data line esd protection * * standard test condition is iec61000?4?2 level 4 test circuit with each pin subjected to 8 kv contact discharge for 1000 pulses. discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. the part is then subjected to st andard production test to verify that all of the tested parameters are within spec after the 1000 strikes. marking diagram device package shipping ? ordering information http://onsemi.com sc?74 (pb?free) 3,000 / tape & reel cm1213a?04so ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. sc?74 so suffix case 318f 1 234m 234 = specific device code m = date code = pb?free package (note: microdot may be in either location) marking diagram ch2 ch1 ch3 ch4 vn vp cm1213a?04so sc?74 (pb?free) 3,000 / tape & reel szcm1213a?04so
cm1213a?04so, szcm1213a?04so http://onsemi.com 2 table 1. pin descriptions pin name type description 1 ch1 i/o esd channel 2 v n gnd negative voltage supply rail 3 ch2 i/o esd channel 4 ch3 i/o esd channel 5 v p pwr positive voltage supply rail 6 ch4 i/o esd channel package/pinout diagrams top view ch2 v p 6?lead sc?74 v n ch3 ch1 ch4 1 2 34 5 6 234 specifications table 2. absolute maximum ratings parameter rating units operating supply voltage (v p ? v n ) 6.0 v operating temperature range ?40 to +85 c storage temperature range ?65 to +150 c dc voltage at any channel input (v n ? 0.5) to (v p + 0.5) v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 3. standard operating conditions parameter rating units operating temperature range ?40 to +85 c package power rating 225 mw functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. electrical operating characteristics (note 1) symbol parameter conditions min typ max units v p operating supply voltage (v p ?v n ) 3.3 5.5 v i p operating supply current (v p ?v n ) = 3.3 v 8.0 a v f diode forward voltage i f = 8 ma; t a = 25 c 0.90 v i leak channel leakage current t a = 25 c; v p = 5 v, v n = 0 v 0.1 1.0 a c in channel input capacitance at 1 mhz, v in = 0 v (note 2) 2.0 pf c io channel i/o ti i/o capacitance 1.5 pf v esd esd protection peak discharge voltage at any channel input, in system contact discharge per iec 61000?4?2 standard t a = 25 c (notes 2 and 3) 8 kv v cl channel clamp voltage positive transients negative transients t a = 25 c, i pp = 1a, t p = 8/20 s (note 2) +9.9 ?1.6 v r dyn dynamic resistance positive transients negative transients t a = 25 c, i pp = 1a, t p = 8/20 s (note 2) 0.96 0.5 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. all parameters specified at t a = ?40 c to +85 c unless otherwise noted. 2. standard iec 61000?4?2 with c discharge = 150 pf, r discharge = 330 , v p = 3.3 v, v n grounded. 3. these measurements performed with no external capacitor on v p (v p floating).
cm1213a?04so, szcm1213a?04so http://onsemi.com 3 performance information input channel capacitance performance curves figure 1. typical variation of c in vs. v in (f = 1 mhz, v p = 3.3 v, v n = 0 v, 0.1 f chip capacitor between v p and v n , 25 c) figure 2. typical variation of c in vs. temp (f = 1 mhz, v in = 30 mv, v p = 3.3 v, v n = 0 v, 0.1 f chip capacitor between v p and v n )
cm1213a?04so, szcm1213a?04so http://onsemi.com 4 performance information (cont?d) typical filter performance (nominal conditions unless specified otherwise, 50 ohm environment) figure 3. insertion loss (s21) vs. frequency (0 v dc bias, v p =3.3 v) figure 4. insertion loss (s21) vs. frequency (2.5 v dc bias, v p =3.3 v)
cm1213a?04so, szcm1213a?04so http://onsemi.com 5 application information design considerations in order to realize the maximum protection against esd pulses, care must be taken in the pcb layout to minimize parasitic series inductances on the supply/ground rails as well as the signal trace segment between the signal input (typically a connector) and the esd protection device. refer to application of positive esd pulse between input channel and ground, which illustrates an example of a positive esd pulse striking an input channel. the parasitic series inductance back to the power supply is represented by l 1 and l 2 . the voltage v cl on the line being protected is: v cl = fwd voltage drop of d 1 + v supply + l 1 x d(i esd ) / dt + l 2 x d(i esd ) / dt where i esd is the esd current pulse, and v supply is the positive supply voltage. an esd current pulse can rise from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec61000?4?2 standard results in a current pulse that rises from zero to 30 amps in 1 ns. here d(i esd )/dt can be approximated by i esd / t, or 30/(1x10 ?9 ). so just 10 nh of series inductance (l 1 and l 2 combined) will lead to a 300 v increment in v cl ! similarly for negative esd pulses, parasitic series inductance from the v n pin to the ground rail will lead to drastically increased negative voltage on the line being protected. the cm1213a has an integrated zener diode between v p and v n . this greatly reduces the effect of supply rail inductance l 2 on v cl by clamping v p at the breakdown voltage of the zener diode. however, for the lowest possible v cl , especially when v p is biased at a voltage significantly below the zener breakdown voltage, it is recommended that a 0.22 f ceramic chip capacitor be connected between v p and the ground plane. as a general rule, the esd protection array should be located as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply, ground planes and between the signal input and the esd device to minimize stray series inductance. additional information see also on semiconductor application note ?design considerations for esd protection?, in the applications section. ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? positive supply rail channel input ground rail chassis ground system or circuitry being protected line being protected one channel of cm1213 d 2 d 1 l 1 l 2 v cc v cl v n v p 0.22 f path of esd current pulse i eso 0 a 25 a figure 5. application of positive esd pulse between input channel and ground
cm1213a?04so, szcm1213a?04so http://onsemi.com 6 package dimensions sc?74 case 318f?05 issue n 23 4 5 6 d 1 e b e a1 a 0.05 (0.002) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318f?01, ?02, ?03, ?04 obsolete. new standard 318f?05. c l 0.7 0.028 1.9 0.074 0.95 0.037 2.4 0.094 1.0 0.039 0.95 0.037 mm inches scale 10:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h e dim a min nom max min millimeters 0.90 1.00 1.10 0.035 inches a1 0.01 0.06 0.10 0.001 b 0.25 0.37 0.50 0.010 c 0.10 0.18 0.26 0.004 d 2.90 3.00 3.10 0.114 e 1.30 1.50 1.70 0.051 e 0.85 0.95 1.05 0.034 0.20 0.40 0.60 0.008 0.039 0.043 0.002 0.004 0.015 0.020 0.007 0.010 0.118 0.122 0.059 0.067 0.037 0.041 0.016 0.024 nom max 2.50 2.75 3.00 0.099 0.108 0.118 h e ? ? l 0 10 0 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 cm1213a?04so/d firewire is a registered trademark of apple computer, inc. ilink is a trademark of s. j. electro systems, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
|
